The present invention relates to a level shift circuit for use in a low power source coupled field effect transistor logic circuit (hereinafter referred to as "LSCFL"), buffered field effect transistor logic circuit (hereinafter referred to as "BFL"), emitter coupled logic circuit (hereinafter referred to as "ECL") or a like circuit. More particularly, it relates to a level shift circuit capable of reducing a power supply voltage and a current needed for an operation of a circuit incorporating this level shift circuit while outputting a desired direct-current voltage level (hereinafter referred to as "DC level").
A LSCFL is used in a variety of circuits because it can utilize a series gating means and operates at a high speed with a low power consumption. A conventional-type LSCFL is shown in FIG. 4 wherein a reference character P denotes a differential logic circuit section comprising an OR circuit formed by field effect transistors (FETs) Q.sub.11 to Q.sub.16 which are connected by using a three level series gate, and a reference character S denotes a level shift circuit section. In this LSCFL, output parts of the differential logic circuit section P are connected to the gates of FETs Q.sub.17 and Q.sub.18, respectively. The drains of these FETs are connected to a power supply terminal V.sub.s while on the other hand the sources thereof are serially connected respectively to diodes D.sub.11,D.sub.12 and diodes D.sub.13, D.sub.14 and grounded through FETs Q.sub.20 and Q.sub.21, respectively, which FETs Q.sub.20,Q.sub.21 generate a constant current.
With this LSCFL the differential logic circuit section P generates logic signals, which are then increased in capability of driving load by the level shift circuit section S. The level shift voltage are outputted to a next circuit (not shown) through output terminals O.sub.1 to O.sub.4 connected respectively to the terminals of the diodes D.sub.11 to D.sub.14. Thus, a logic circuit is formed as a whole. In this case, in order to obtain three DC levels, it is conceivable to obtain one DC level from output terminals A and B provided before the diodes D.sub.11 and D.sub.13, respectively. However, DC levels at output terminals A and B are almost the same as those of the gate electrodes of the FETs Q.sub.17 and Q.sub.18, respectively. Hence, the respective DC levels of the terminals A and B are instable due to current to voltage characteristic (hereinafter referred to as I-V characteristic) of a FET, like a I-V characteristic in rise of a triode. This results in a difficulty of obtaining a DC level which assures a stable operation of the circuit.
There has been introduced a level shift circuit which can reduce the series voltage of the level shift circuit section S governing the power supply voltage so as to operate a LSCFL with a low power supply voltage, in "Level Shift Circuits for GaAs Low Power Source Coupled FET Logic", The Transactions of the IEICE, VOL. E 70, NO. 4 April 1987, pages 224 to 226. This circuit is shown in FIG. 5 wherein FETs Q.sub.31 to Q.sub.34 are used instead of the diodes D.sub.11 to D.sub.14 in the level shift circuit section S, and the FETs Q.sub.31 and Q.sub.32 as well as the FETs Q.sub.33 and Q.sub.34 are connected to each other in series with respective gate which is connected with drain. In the level shift circuit, each diode conventionally requires a level shift voltage of about 0.7 V, while the introduced level shift circuit can provide the same current intensity as with the conventional one, with each FET requiring a level shift voltage of only about 0.4 V. As a result, the power supply voltage needed for the introduced level shift circuit is less than that for the conventional one by 1.8 V, or by 30% in total.
The LSCFL, despite its large power consumption, is employed in various circuits in view of its wide applicability to devices which are different in electric characteristics. With the recent trend of compact and lightening electronic devices, however, the LSCFL is being required to operate at a low supply voltage.
In this respect, with the conventional level shift circuit using diodes it is difficult to reduce power supply voltage and operating current since current always needs to flow in the circuit. Further, since a saturation voltage for each diode cannot be reduced to less than 0.7 V without the loss of operation speed, the power supply voltage in total cannot be reduced because of serial connection of diodes though this circuit can cause other circuit associated with the LSCFL to operate at a relatively low voltage. In addition, there is another problem that the amount of level-shifting cannot be set to a desired value because it depends on the semiconductor material used for each diode and, hence, cannot be varied.
With the above-mentioned level shift circuit using FETs in which the respective gates are short-circuited with drains, current always needs to flow in the circuit as with the above circuit using diodes. Although this circuit can substantially reduce the power supply voltage, the voltage-current relation in this circuit is instable due to variation in characteristics of the FETs, particularly static characteristics such as threshold voltage V.sub.th and current amplification factor since a FET operation is similar to a triode operation in rise in a transient state. This results in a substantial instability in a level-shifting amount of output at each unit level shift circuit, resulting in a problem of extremely poor controllability in level shift voltage.
The present invention has been attained in view of the foregoing circumstances. Thus, it is an object of the present invention to provide a novel level shift circuit capable of obtaining a stable level-shifting amount while operating at a low power supply voltage.